1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly to an array substrate for a liquid crystal display device having good contact property and high aperture ratio.
2. Description of Related Art
Generally, conventional liquid crystal display (LCD) devices include upper and lower substrates with liquid crystal molecules interposed therebetween. The upper and lower substrates are generally referred to as a color filter substrate and an array substrate, respectively. The upper and lower substrates respectively include electrodes disposed on opposing surfaces of the upper and lower substrates. An electric field is generated by applying a voltage to the electrodes, thereby driving the liquid crystal molecules to display images depending on the light transmittance.
Among the different types of known LCDs, active matrix LCDs (AM-LCDs), which have thin film transistors and pixel electrodes arranged in a matrix form, are the subject of significant research and development because of their high resolution and superiority in displaying moving images. The conventional AM-LCD devices, in which the liquid crystal layer is driven by the electric field perpendicular to the upper and lower substrates, have a high transmittance and a high aperture ratio and the common electrode of the upper substrate is grounded so that the break of the devices due to the static electricity can be prevented.
On the other hand, the lower substrate of the LCD device is formed by repeatedly depositing and etching the thin film layer. Usually, the number of masks used in photolithography processs is about 5 or 6 and represents the number of processes.
FIG. 1 is a schematic plan view of an array (lower) substrate for a conventional LCD device and FIG. 2 is a schematic cross-sectional view taken along a line “II-II” of FIG. 1.
In FIGS. 1 and 2, a gate line 21 along a row direction and a gate electrode 22 extended from the gate line 21 are formed on a substrate 10. Then, a gate insulator 30 is formed on the gate line 21 and the gate electrode 22. Subsequently, an active layer 41 and an ohmic contact layer 51 and 52 are formed on the gate insulator 30. On the ohmic contact layer 51 and 52, a data line 61, source and drain electrodes 62 and 63 and a storage electrode 65 are formed. The data line 61 is disposed perpendicular to the gate line 21, the source electrode 62 is extended from the data line 61, the drain electrode 63 is facing and spaced apart from the source electrode 62, and the storage electrode 65 overlaps the gate line 21. The data line 61, source and drain electrodes 62 and 63 and the storage electrode 65 are covered with a passivation layer 70 having first and second contact holes 71 and 72. The first and second contact holes 71 and 72 expose the drain and storage electrodes 63 and 65, respectively. A pixel electrode 81 is formed on the passivation layer 70 at a pixel region defined by the gate and data lines 21 and 61. The pixel electrode 81 of indium-tin-oxide (ITO) or indium-zinc-oxide (IZO) is connected to the drain and storage electrodes 63 and 65 through the first and second contact holes 71 and 72, respectively.
In the fabricating process of the array substrate discussed above, the first and second contact holes 71 and 72 are formed by depositing and patterning the passivation layer 70. However, during the photolithography and etch process, the passivation layer can be contaminated by organic materials due to the incomplete drying after etching and cleaning process or impurities of the fabrication apparatus. In the following deposition process of ITO for the pixel electrode 81, this contamination weakens the adhesion between the passivation layer 70 and ITO film so that the etching solution for ITO film can permeate into the interface of the passivation layer 70 and ITO film. Therefore, the drain electrode 63 under the first contact hole 71 is easily corroded by the etching solution and the electric open circuit is created between the drain and pixel electrodes 63 and 81.
Moreover, since the drain and pixel electrodes 63 and 81 are connected through the first contact hole 71, a portion of the drain electrode 63 overlapping the pixel electrode 81 should have an area larger than a specific value. However, since the drain electrode 63 is opaque, the larger the area of overlapping drain electrode is, the lower the aperture ratio will be.